It is a simple, bidirectional two-wire synchronous serial bus and requires only two wires to transmit information between devices connected to the bus.However, it is not used for PC-device communication but instead with modules and sensors. It is a serial communications protocol similarly to UART.

Stands for Inter-integrated-circuit (I2C).As long as the UART is initialized, the interrupt routine will do everything automatically. Data loss would not occur as a result of the FIFO as it has already foreseen any problems in the process of sending and receiving.Using UART communication, the interrupt mode is simpler and more efficient than the polling method. With no transceiver FIFO, each data will be interrupted once and become inefficient. With a transceiver FIFO, it can generate an interrupt and constantly transmit and receive data (up to 14), which improves the transmission and reception efficiency. The transceiver FIFO is to solve the issue regarding the CPU being inefficient and the UART transceiver being interrupted too frequently.

When the hardware receives the data, it will be stored into the receiving FIFO. The program will retrieve and erase the data automatically from the receiving FIFO, so there will be space in the receiving FIFO. If the data in the receiving FIFO is not erased and the receiving FIFO is full, the data will be lost.

When a complete data packet is received, the data is stored in the receiving FIFO.

If RX is high, a valid stop bit will be acknowledged.

If the start bit is valid, data bits are sampled every 16th cycle of Baud16 based on the length of the data character. If the parity mode is enabled, the parity bit is also detected.

If RX is still low during the 8th cycle of Baud16 while the start bit is valid, it would be processed as the wrong start bit and thus ignored.

When the UART receiver is idle and if the data input is low after start bit is received, the receive counter will start running and expect to receive data in the 8th cycle of BAUD16.

The ‘BUSY’ bit will only be inactive after data is finished transmitting, the FIFO is emptied and every bit has been transmitted including the stop bit.

It’s a UART buffer that that forces each byte to be passed in sequence to the receiving UART.

Once data is being transmitted by the transmit FIFO, the FIFO ‘BUSY’ flag will be asserted and active during the process.

2 wire library for stm